This article talks about why good cycle time matters for semiconductor wafer fabs, why good cycle time is difficult to achieve, and what fab managers should do at a high level to improve it. We believe that a three-pronged approach is necessary to improve fab cycle times.
In this article, we introduce The Waddington Effect, a condition in which doing scheduled maintenance can sometimes cause a short-term increase in unscheduled downtime. We discuss whether the Waddington Effect contradicts our advice to separate maintenance events rather than grouping them, as well as how to generate and use Waddington Effect Plots.
The Metrology Sampling Optimizer (MSO) is designed to handle baseline metrology sampling using either time or percentage rules. Beyond baseline sampling, rules may be configured to handle event-based sampling.
Product Introduction and Benefit
In the early days of semiconductor manufacturing, "scheduling" meant teams of people poring over lot lists and routes discussing how to run WIP for the day.
Following the success of FDC solutions in front-end wafer processing, several semiconductor manufacturers have chosen to implement FDC in their back-end wafer assembly processes.
A well-configured FDC system requires intimate knowledge of processes, equipment, and failure modes as well as a concerted effort to setup and maintain the system. Even when it is fully set up, it is only as good as the fault conditions that have already been conceived.
Captures the portion of utilization that drives cycle time at the tool level by distinguishing between standby time with WIP waiting and standby time when no WIP is waiting.